Computational Dialectics: where is D1-B Gate B?

An independent research track

Computational Dialectics runs independently from DEVİM model training. The goal is not to attach philosophical names to modules, but to make mechanisms such as revision, relation change and preservation explicit and falsifiable.

Current phase

D1-B Gate B — Preregistration / Learned Pilot Protocol. Gate-A v2 and Gate-B v5 design are frozen. PyTorch implementation v3 passed the strict CPU/static/runtime preflight 22/22, and a fresh independent implementation review returned PROCEED.

Why is there still no training?

Before any scores are seen, dataset splits and hashes, seeds, optimizer/LR schedule, update budget, checkpoint rule, primary metrics, decision margins, abort rules and compute ceiling must be frozen.

Otherwise an apparent M0 advantage could be explained by tuning or researcher degrees of freedom.

Current blocker

The blocker is no longer theory or implementation. It is preregistration and fairness discipline. No optimizer step is authorized until that gate closes.

Claim boundary

There is no claim yet of dialectical intelligence, unrestricted Transformer superiority, or a proven alternative architecture. What exists is a set of increasingly controlled, testable mechanisms.